1. Field of the Invention
This invention relates to improvements in computer systems, or the like, and more particularly to improvements in memory management hardware and techniques, and still more particularly to improvements in methods and apparatuses for providing a computer system containing both dynamic random access memory (DRAM) and enhanced dynamic random access memory (EDRAM) components, and still yet more particularly to providing a computer system having a combined cache for both DRAM and EDRAM components of a combined memory.
2. Background of the Invention
The performance of computer central processing units (CPUs) has increased dramatically in recent years, exceeding that of corresponding increases in the performance of the DRAM devices typically used in conjunction with such computer CPUs. Not until the introduction of cache memory techniques was the performance of systems with DRAM main memory improved. This performance improvement was achieved by making a high speed, locally accessed copy of all or part of the contents of the DRAM main memory available to the CPU in high speed memory devices, so that even during memory accesses the CPU did not always need to operate at the slower speeds of the system bus or the DRAM main memory.
Such caching methods of memory management are typically implemented with a secondary cache for the DRAM main memory (sometimes referred to as an "L2" cache.) The advantages of caching are made possible by virtue of the fact that many of the memory accesses by the CPU are in highly repetitive memory address spaces. Typically, once the repetitive address spaces are copied from the memory to the cache, they can be utilized through many bus cycles before needing to be updated with the contents of subsequent memory addresses to be accessed. Memory caching is advantageous particularly for read cycles of the computer, which, in contrast to the write cycles, constitute 90% of the external accesses of the CPU.
The most popular hardware realization of a cache memory system incorporates a high speed SRAM cache and a slow, less expensive DRAM main memory. The DRAM main memory is usually located on the system bus, and the SRAM cache is usually provided by a cache chip set located on a local bus. The chip set provides a cache directory, a cache controller, and a cache memory. The cache directory is connected to the local address bus by tag (upper address bit) lines and set (lower address bit) lines, and contains a list of main memory addresses which are copied to the cache data memory. The cache directory is also connected to the cache controller, which implements the algorithm to move data into and out of the cache data memory and the cache directory. The cache data memory, which is connected to the local bus, provides a fast memory, usually SRAM, used to store replicas of selected data from the main memory.
In addition, recently EDRAM devices have been introduced to eliminate the external SRAM caching facility in computer systems. EDRAMs are enhanced DRAM devices that incorporate both SRAM and DRAM devices onto a single chip, and are described in greater detail below.
To date, the lack of a suitable caching system that includes both DRAM and EDRAM components has retarded development of low cost hybrid main memory systems combining the speed advantages of EDRAM with the cost advantages of DRAM. What is needed, therefore, is a way to combine DRAM and EDRAM memory components, while at the same time realizing the caching benefits of EDRAM over the entire memory map.